Hardware software partitioning of control data flow graph on system on programmable chip

Description: A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist on memories, one or more microprocessors, interface devices, configurable logic blocs and other necessary components to achieve the intended function. In this work we aim to propose a new hardware-software partitioning algorithm of control data flow graph for SOPC. The main aim the algorithm is to find a best trade-offs between hardware and software implementation of operations in order to satisfy design constraints in term of latency and hardware resources of the target application physical constraints in hw-sw partitioning for architectures with partial dynamic reconfiguration, ''complex dynamic programming algorithm for hardware/software partitioning,'' Information processing letters, vol. 98, no. 2, pp. 41–46, 2006.